This invention relates to a memory management technique using a hierarchal memory system and to a technique which is particularly effective when applied to buffer memory devices. For instance, the present invention relates to a technique which is effective when utilized for a cache memory structure in a data processing system employing a buffer memory system.
In conventional microcomputers employing a buffer memory system, data having a high frequency of use among the data stored in a main memory, consisting of a dynamic RAM, are kept in a cache memory and are controlled by memory management means called a "cache controller" in order to improve through-put.
In the conventional buffer memory system, however, the cache memory consists of a general-purpose static RAM and the cache controller is provided as an external circuit to the CPU (central processing unit).
Moreover, access to the cache memory is made after the cache controller determines whether or not the data required by CPU exists in the cache memory.
Therefore, access is slowed by the time required for the determination by the cache controller, in comparison with the time required when the CPU makes direct access to the cache memory. In addition, the gate delay time in the cache controller or logic circuits implemented as peripheral circuits to the cache memory is also lengthened, and the cache access cycle correspondingly longer.